The levels of Verilog

• Switch level
• Gate level
• Dataflow (RTL) level
• Behavioral level

This means that my world will be somewhat simpler. I will indeed use dataflow (i.e. "assign" statements) along with behavioral level coding (initial and especially "always" blocks.

If you take some good advice and restrict your use of initial blocks entirely to simulation, you will find that all of your behavioral code will be inside of always blocks. It must be. This is where you find blocking and non-blocking assignment.

As for gate level, why should I write cumbersome gate instantiations when I could instead just write boolean logic in assign statements? I would certainly rather write the following than to instantiate a bunch of gates:

	assign out = (a & b & c) | (a & ~b & ~c);