Vivado EMIO project with the new Vivado 2024.2

I launch vivado and start from scratch with a new project I call "s9_emio". The create project wizard looks all the same. I create a block diagram and add the Zynq block. It all looks familiar and exactly the same so far.

I work up a constraint file with all of the IO pins I want to connect to EMIO. I get 51 of them including the 4 on-board LEDs. I call this "emio_all.xdc". To add it, I go to "sources", click on the big "+", change the selection to "add or create constraints". Next takes you to "add file" then you get a filesystem browser. I go to:

/u1/Projects/Zynq/Antminer

Now, back to the Zynq block. Double click to customize it.

• Under PS-PL configuration we turn off the AXI GP0 interface (see AXI non-secure)
• Under MIO, under GPIO find EMIO and change width from 64 to 51

A thing that is labeled "GPIO_0" appears on the block diagram. This is the 51 EMIO signals. Click to get a menu, and select "make external".

Run block automation and it makes connections to DDR and fixed_IO. We could have switched off ethernet, but having those connections that we don't intend to use should not hurt.
Now the design work is done!

Build it

Now run Synthesis. Wait for the popup to tell you it is done. Keep an eye on the "progress" status in the upper right. Watch for scary messages in the Tcl Console at the bottom.
Success!

Now run Implementation. Watch the popup when it finishes because it will default to "open implemented design" -- we want "generate bitstream" instead.

If we get this far without errors we won't have problems generating the bitstream. Well, that is what I thought, but it failed. I am betting on errors with the constraint file.

Fix my errors

Indeed, I find the information I want under "Messages". It says that "set_property" expects at least one object and it names emio_all.xdc and elsewhere I see: "No ports matched 'GPIO_0_tri_io[0]'.

So the problem is that get_ports is returning a null. Here is a line from my bad constraint file

set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_tri_io[0] }];

The bottom line is that I need to figure out what the name of these ports is. I look at the Verilog for my HDL wrapper and see:

inout [50:0]GPIO_0_0_tri_io;

set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_0_tri_io[0] }];

Now I run Synthesis again, and implementation, and now it finds a stupid error in my Constraint file. I have a typo placing io-25 and io-22 on the same device pin. I edit the constraint file again, changing W15 to U15 for io-25.
Then rerun everything and ....

And we have a bitstream!

/u1/home/tom/vivado/s9_emio/s9_emio.runs/impl_1/design_1_wrapper.bit

Conclusion