The READ and WRITE signals go to various LS138 chips. The WRITE signal goes to 3 of them. The READ signal goes to one of them, as well as to both PAL devices -- to pin 11 on U35 and to pin 6 on U33.
The 2E0 signal goes to pin 8 on GAL U33. Inside the PAL, the signal simply gets inverted and goes out on pin 19 as "ADR_LOCK, which drives the clock on U36 which is an HCT273. So this 273 is what latches the "select" byte written to 0x2e0. The clock is active on a rising edge.
So the 2E0 signal is clearly active low and latches data into U36.
The write signal for 2E2 "WRITE" has nothing to do with either PAL. It enables the gang of three LS138 chips (U30, U38, U39) The address info for these is the low 3 bits (A0,A1,A2) from the 273 latch just discussed. Which of these three LS138 is active is determined by signals from the U35 PAL, namely from pins 13 (for U39), 18 (for U38), or 19 (for U30).
/cs2_u39 = a7*a6*a5*a4*/a3*reset cs2_u39.oe = vcc /cs2_u38 = a7*a6*a5*/a4*a3*reset cs2_u38.oe = vcc /cs2_u29_30 = a7*a6*a5*/a4*/a3*reset cs2_u29_30.oe = vccSo we have the following:
U29 - reads from 0xE0 .. 0xE4 U30 - writes to 0xE0 .. 0xE7 U38 - writes to 0xE8 .. 0xEF U39 - writes to 0xF0 .. 0xF7The READ and WRITE signals for 2E2 on the cable are also active low.
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