Zynq - MIO

The above diagram looks hopelessly complex, but rewards careful study. It can be found on page 49 of the TRM.

The right side shows "outside world" connections -- 54 of them.

Notice that GPIO is just one of many players. Take note of downward pointing arrows, indicating that it is possible to route given signals to EMIO (and thus to and possibly through the PL). By no means is it possible to route any subsystem through the EMIO.

The missing aspect of this is the mux control for MIO. This can be found on page 52 of the TRM in what is called the "MIO at a glance" table. This shows you the possibilities. The actual selection is made via the MIO pin registers in the slcr, as discussed below.

A vital part of the puzzle is the MIO pin control registers which are among the SLCR (system level control registers). See the TRM on page 1570, in particular pages 1631 and the following. These are 32 bit registers where only the low 14 bits are used. Bits 7:2 are the Mux select bits which control which actual device is connected to the pin in question.

There are 54 of these registers (one per MIO pin). They start at address 0xf800_0700.