Xilinx Zynq - XC7Z010 - FPGA Overview

The XC7Z010 has an ARM side and an FPGA side. The literature calls these the PS and PL respectively. If you think of "PL" = programmable logic, you will remember. These pages deal with the FPGA side

The PL can be entirely powered down. When it is powered up, it needs to be loaded with a bitstream. For this particular device this is 16,669,920 bits (about 2 megabytes). There is an XADC device that lives within the PL, but can be used without configuring the PL. The PL includes (among many other things) 60 ram blocks, each 36K in size.

There are several ways to load the bitstream. One was is for the PS to load it via the "PCAP" interface. There are registers in the "devC" (aka devconfig) such as around 0xf8007000 that you should look at to understand this.

What is inside the thing

• Wikipedia: list of Xilinx FPGAs

28,000 logic cells
35,200 flip flops
17,600 LUTs
60 block ram (36K each)
80 DPS slices
will do 100 GMAC/s
Two 12 bit 1M sps ADC with up to 17 differential inputs

It can do 100 GMAC/s, where a GMAC is a "Gig" of MACs, where a MAC is a multiply-accumulate operation. They say that each DSP48 block in a Virtex7 has a preadder, so the block does 2 MAC's in a cycle.
So max GMACS = 80 DSP * 2 * clock, where the clock is 625 Mhz.

Xilinx has 4 lines of FPGAs. All with the "-7" designation use their 28nm process.

• Spartan - for low cost, high volume
• Artix - for lower power and cost
• Kintex - mid range
• Virtex - top end.